Semiconductor Design Services


Our highly experienced team has successfully taped out many IPs, subsystems and chips of varying complexities, power and speeds for industrial, automotive, medical, consumer applications within short time to market.

We help semiconductor companies to achieve the highest ROI by maximizing the productivity, reducing engineering cost, process costs and with a short time-to-market. We leverage our custom process, suite of tools and platforms to create rapid solution development and deployment for our customers.

RTL Design & Verification Engineering

Eldaas Technologies has highly experienced ASIC/SOC/FPGA verification services and solutions design teams and has successfully taped out many IPs, subsystems and chips. Our RTL design, ASIC and AMS Verification Services, and Gate Level Simulation help you achieve an effective bug-free design with our strong expertise in Design &Verification, associated tool flow, combined with a strong understanding of peripheral system level deployment and industry standard verification methodologies.

Key Offering
  • RTL Design
  • Ip And Soc Verfication
  • Environment Architecture
  • Coverage Driven Test Plans
  • Low Power Expertis
  • Static Formal Verification
  • System C Modeling
  • Gate level Simulation
Physical Design

Our team of dedicated subject matter experts with rich and diverse experience in the physical design flow and methodologies helps our designs achieve optimum performance, power, and area (PPA). Eldaas’s proven flows and methodologies ensure that the design passes the range of foundry specific Design rules and constraints to avoid multiple iterations to avoid delays and stay on schedule.

Key Offering
  • Physical Architecture
  • RTL Synthesis & Pre-Layout STA
  • Design for Test (Scan, ATPG, MBIST, LBIST)
  • Design Partitioning
  • Full-chip timing/SI/PI closure,Static Timing Analysis
  • Timing Convergence
  • Fullchip Assembly, Sign-Off Checks & Tape-out
DFT & ATE Engineering

Our DFT services consists of scan insertion from block level to top level designs, ATPG pattern generation, pre/post silicon validation, memory built in self-test (MBIST) and JTAG for complex design

Key Offering
  • DFT Planning & Architecture
  • DFT Implementation
  • ATPG , ATPG verification, ATE patterns & Silicon debug
  • MBIST Verification ,ATE patterns and silicon debug
  • Boundary SCAN Verification, ATE patterns and silicon debug
  • ATE Test Program Development & Production Support
  • ATE Hardware development and packaging
Emulation & Prototype

Our team has carried out Emulation of complex multi-million processor based SoCs for leading semiconductor companies and supported the bring-up of software on a pre-silicon Emulation platform with their expertise in Synopsys Zebu/HAPS, Mentor Veloce and Cadence Palladium emulation platforms. Eldaas Emulation and FPGA design [Xilinx, Altera and Microsemi ]have hands-on experience doing the following activities at several of our clients.

Key Offering
  • FPGA prototyping
  • Processor based emulation
  • FPGA design
Analog Design

Eldaas team has been involved been involved in layouts on many analog and mixed-signal chips . Our Layout expertise includes In-depth expertise on RF, SerDes, PMUs, RF designs, Memories, Data Converters, and IOs. Our Analog and Mixed Signal(AMS) expertise includes both modelling and verification.

Key Offering
  • Block level and full chip layouts
  • Floor planning, Placement, Routing
  • Matching transistor pairs
  • Shielding critical nets
  • EM&IR analysis and repair
  • DRC/LVS
  • Expertise in Data Converters, IOs, Clocking Circuits (PLL, DLL), Serdes, Memories, PMUs and RF layouts
  • Expertise in Bulk CMOS, SOI and BCD processes