Introduction:

Ethernet is a Link Layer Protocol in the TCP/IP protocol stack between the physical and data link layer. It is the most widely used protocol for Local Area Networks (LANs). Every device on Ethernet is assigned a unique MAC address for communication. Gigabit Ethernet refers to various technologies developed for transmitting Ethernet frames at the rate of gigabits per second. The Reduced Gigabit Media-Independent Interface (RGMII) is used to interface Ethernet IP core on FPGA. The Media Access Layer converts the packets into a stream of data to be sent while the Physical Layer converts the stream of data into electrical signals. RGMII provides a media-independent interface so that there is compatibility between MAC and PHY irrespective of the hardware used. In this tutorial, our custom board is used to demonstrate a TCP/IP echo server application. The echo server application runs on light-weight IP (lwip) TCP/IP stack.

Prerequisites:

  • Hardware:
    • Xilinx 7 series FPGA based custom board
    • Cross over Ethernet Cable
    • Xilinx Platform Cable USB II JTAG
    • USB 2.0 B-type cable for debug port
  • Software:
    • Xilinx Vivado Design Site 2018.2 or later
    • Telnet Application
    • Serial Terminal (Putty, Tera Term, etc.)

Problem statement:

Most of the Ethernet designs in Vivado are using DDR3 memory. In this article we are going to design Ethernet using Asynchronous SRAM from alliance memory by using AXI EMC IP core from Xilinx Inc.

Steps for Designing Ethernet using AXI EMC IP core:

Step 1:

  • Open Vivado Design Suite; go to File->New Project. The “New Project” window will open. Click “Next”.

Figure 1: Creating a project

Step 2:

  • Enter a name for the project and save it at a suitable location. Select the option “Create project subdirectory”. Click “Next” to continue. In the project location spaces are not allowed.

Figure 2: Creating a project Name

Step 3:

  • In the “Project Type” window, select “RTL Project”

Figure 3: Selecting a project Type

Step 4:

  • Select the Required FPGA part number in Search Box. Click “Next” to continue.

Figure 4: Selection of Suitable FPGA

  • Click “Finish” to complete creating a new project. A new project will be created by Vivado with the selected settings.

Step 5:

  • Under “Flow Navigator” panel, select “Create Block Design” under “IP INTEGRATOR”. Enter a name for the block design and click “OK”. An empty block design will be created.

Figure 5: Creating a Design

Step 6:

  • Add mircoblaze into the IP integrator. And then Click on Run block Automation.
  • Then Add the UART using the AXI Uartlite IP core and then click on “Run Connection Automation”.
  • Micro Blaze IP core Settings:

Figure 6: Mircoblaze Settings

Figure 7: Block Design for UART

Step 7:

  • In Diagram Window Add the AXI EMC IP core and add the timing parameters of the SRAM asper the datasheet and user guide of AXI EMC.
  • Click on “Run Connection Automation” and Connect AXI EMC rd _clk to s_axi_clk

Figure 8: Block Design for ASRAM

Step 8:

  • Add AXI 1G/2.5G Ethernet Subsystem and AXI Timer into IP integrator. Configure Ethernet subsystem using DMA.
  • Configuration Settings of Ethernet Subsystem:
  • Select Ethernet Speed is 1Gbps and Physical interface selection is “RGMII”.

Figure 9: Physical Interface Settings of Ethernet Subsystem

  • Select MAC Features, Check TX and RX memory size should be 4K and TX and RX checksum offload both should be NO CHECKSUM OFFLOAD.
  • In MAC Features -> Enable the Enable static Counter options  and Static counter width is 32-bit in Statistics counter options         
  • Remaining features keep Default all the options.

Figure 10: MAC Feature Settings of Ethernet Subsystem

  • Click on “Run Block Automation”.
  • Route the following connections to the inputs of Concat block (order does not matter):
    • interrupt on AXI Uartlite block
    • interrupt on AXI Timer block
    • mm2s_introut and s2mm_introut on AXI Direct Memory Access block
    • interrupt and mac_irq on AXI 1G/2.5G Ethernet Subsystem

Figure 11: Block Design of Ethernet using ASRAM

Step 9:

  • Select “Validate Design” option from Tools menu to make sure the design and its connections are correct.

Figure 12: Validating the Block Design

Step 10:

In the Sources window right click on the design and select “Generate output products”.

  • Select to generate output products, each IP core at the out of box. This will reduce the synthesis time.
  • Select “Create HDL Wrapper”. Click “OK” in the dialog box that appears.

Step 11:

  • Select “Run Synthesis” followed by “Run Implementation”. If the design is implemented successfully, select “Generate Bit stream”.

Figure 13: Process for Generating Bitstream

Step 12:

  • After generating the Bitstream successfully, select “Export -> Export Hardware” from the File menu. Select “include Bitstream” checkbox and click “OK”. This will generate .hdf file. It will be used as input to SDK.

Figure 14: Launch SDK

Step 13:

  • Select “Launch SDK” from the File menu. Select workspace as “Local to project” and click OK to launch the Xilinx SDK.

Step 14:

  • Select “Application Project” from the File menu. Type in a project name, select hardware platform and click “Next”.

Figure 15: Create a project in SDK

Step 15:

  • At this point, your SDK workspace should contain only the hardware description and no applications:
  • Select “lwip Echo Server” template from the list of available templates and click “Finish”.

Figure 16: Create a project with lwip Echo server

Step 16:

  • Select “Board Support Package Settings” from the “Xilinx” menu. Select lwip library, change the “dhcp options” to “false” and ensure that “debug options” are “false”.

Figure 17: Board Support Package Settings

  • Select “phy_link_speed” in temac_adapter_options as “Config_linkspeed Automatically”.

Figure 18: Board Support Package Settings

  • After changing the library settings, click “OK”. SDK will update the BSP automatically. If that didn’t happen for any reason, run a build manually.

Step 17:

  • Once the build is completed successfully, power up the custom board using external DC power supply and connect Xilinx Platform USB cable to the board.

Step 18:

  • Program the FPGA on Custom board with a simple boot loop program by selecting the “Program FPGA” option from the “Xilinx” menu.

Figure 19: Programming FPGA

Step 19:

Open the

  • Open the Suitable COM port in any serial terminal (Putty, Tera Term, etc.) with baud rate 115200. 
  • Now, right click on the .elf file in the Project Explorer and select “Launch on Hardware” as shown below.

Figure 20: Run or Debug the Project

Step 20:

  • Observe the details displayed on the serial terminal.

Figure 21: Serial Port (Terminal)

  • Open the Control Panel -> Network and Internet->Network Connections.
  • Right Click on Ethernet Connection ->Properties->Click on Internet Protocol Version 4 (TCP/IPv4).

Figure 22: Network Connections

  • Internet Protocol Version4 (TCP/IPv4) properties GUI will be open.

Figure 23: Ethernet Properties

  • In General -> Enable the Use the following IP address and then enter the
    • IP address to 192.168.1.30
  • Subnet mask in code and the settings should match.
  • We will get a warning symbol on selected Ethernet Connection.
  • Now open the command prompt then ping with the respective IP address using Ping command i.e., ping 192.168.1.10

Figure 24: Ping the IP address in Command Prompt

Figure 25: Ping result